1. Field of the Invention
The present invention generally relates to a damascene structures for integrated circuits and, more particularly, to a method of forming a dual damascene structure comprising dielectric materials having low dielectric constants (low K).
2. Description of the Related Art
Integrated circuits have evolved into complex devices that can include millions of components (e. g., transistors, capacitors and resistors) on a single chip. The evolution of chip designs continually requires faster circuitry and greater circuit density. The demands for greater circuit density necessitate a reduction in the dimensions of the integrated circuit components.
As the dimensions of the integrated circuit components are reduced (e. g., sub-micron dimensions), the materials used to fabricate such components contribute to their electrical performance. For example, low resistivity metal interconnects (e. g., copper and aluminum) provide conductive paths between the components on integrated circuits.
Copper is particularly advantageous for use in interconnect structures due to its desirable electrical properties. Copper interconnect systems are typically fabricated using a damascene process in which trenches and vias are etched into dielectric layers. The trenches and vias are filled with copper, which is then planarized using, for example, a chemical-mechanical planarization (CMP) process.
Copper interconnects are electrically isolated from each other by an insulating material. When the distance between adjacent metal interconnects and/or the thickness of the insulating material has sub-micron dimensions, capacitive coupling potentially occurs between such interconnects. Capacitive coupling between adjacent metal interconnects may cause cross talk and/or resistance-capacitance (RC) delay which degrades the overall performance of the integrated circuit. In order to reduce capacitive coupling between adjacent metal interconnects, low dielectric constant (low k) insulating materials (e. g., dielectric constants less than about 4.0) are needed.
Unfortunately, low K dielectric materials are not easy to process using damascene and dual damascene techniques. In particular, low K dielectric materials are susceptible to damage during plasma processing, such as plasma etching used to strip photoresist layers after the low K dielectric layer has been etched. Furthermore, low K dielectrics are prone to have adhesion problems, i.e., the low K materials do not effectively adhere to underlying layers.
In the prior art, dual damascene structures are formed in a film stack comprising a copper contact, a passivation layer, a first low K dielectric layer, a dielectric cap layer, and a second low K dielectric layer. A hard mask is deposited and patterned using a photoresist to define a via location. The hard mask is used to etch a via into the second dielectric layer down to the dielectric cap layer. A second photoresist patterning process is performed to define a trench pattern in the hard mask. During the patterning process the cap layer is removed from the bottom of the via. Next, the second low K dielectric layer is etched to form a trench, while simultaneously, the via is extended through the first low K dielectric layer down to the passivation layer. The cap layer protects the first low K dielectric from etching at the bottom of the trench and forms a mask for the via. The passivation layer at the bottom of the via and the cap layer at the bottom of the trench are then removed. Lastly, the trench and via are filled with metal, e.g., copper, to complete the dual damascene structure.
The process of the prior art is fraught with difficulties. The use of a cap layer to protect the low K dielectric during trench etch complicates the process by requiring additional deposition and etch processing. Furthermore, the process requires two photoresist or hard mask patterning steps. Also, it is difficult to find suitable etch stop layers and hard mask layers that have both good etch selectivity with respect to the low K dielectric layer and sufficiently low dielectric constants themselves. Furthermore, it is difficult to achieve these goals without creating a process that is overly complex or requires the use of numerous processing chambers.
Therefore, a need exists in the art for simplified methods of accurately fabricating low K damascene structures.